Field
Embodiments of the present disclosure generally relate to methods of manufacturing a vertical type semiconductor device, and more particularly to methods of manufacturing a hardmask layer for manufacturing a vertical type semiconductor device.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
Furthermore, the demands for greater integrated circuit densities also impose demands on the process sequences used in the manufacture of integrated circuit components. For example, in process sequences that use conventional photo lithographic techniques, a layer of energy sensitive resist is formed over a stack of material layers disposed on a substrate. The energy sensitive resist layer is exposed to an image of a pattern to form a photoresist mask. Thereafter, the mask pattern is transferred to one or more of the material layers of the stack using an etch process. The chemical etchant used in the etch process is selected to have a greater etch selectivity for the material layers of the stack than for the mask of energy sensitive resist. That is, the chemical etchant etches the one or more layers of the material stack at a rate much faster than the energy sensitive resist. The etch selectivity to the one or more material layers of the stack over the resist prevents the energy sensitive resist from being consumed prior to completion of the pattern transfer. Thus, a highly selective etchant enhances accurate pattern transfer.
As the geometry limits of the structures used to form semiconductor devices are pushed against technology limits, the need for accurate pattern transfer for the manufacture of structures having small critical dimensions and high aspect ratios and structures with different materials has become increasingly difficult to satisfy. For example, the thickness of the energy sensitive resist has been reduced in order to control pattern resolution. Such thin resist layers (e.g., less than about 2000 Å) can be insufficient to mask underlying material layers during the pattern transfer step due to attack by the chemical etchant. An intermediate layer, called a hardmask layer, is often used between the energy sensitive resist layer and the underlying material layers to facilitate pattern transfer because of its greater resistance to chemical etchants. Conventionally, silicon oxynitride, silicon carbine or carbon films are often the materials utilized for the hardmask layer.
During etching, the hardmask layer utilized to transfer patterns to the materials is exposed to aggressive etchants for a significant period of time. After a long period of exposure to the aggressive etchants, the hardmask layer without sufficient etching resistance may be dimensionally changed, resulting in inaccurate pattern transfer and loss of dimensional control. Furthermore, the similarity of the materials selected for the hardmask layer and the adjacent layers disposed in the film stack (such as the repeating layers in a film structure utilized for manufacturing stair-like three dimensional NAND devices) may also result in similar etch properties therebetween, thus resulting in poor selectivity during etching. Poor selectivity between the hardmask layer and adjacent layers may result in non-uniform, tapered and deformed profile of the hardmask layer, thereby leading to poor pattern transfer and failure of accurate structure dimension control.
Thus, there is a need for an improved hardmask layer for structures with accurate profiles and dimension control, particularly, for three dimensional (3D) stacking of semiconductor devices.